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.This invention relates generally to semiconductor integrated circuit (IC) static memory devices and, more particularly, to an improved circuit arrangement for permitting easy access to one of a multiplicity of pairs of complementary doped regions formed in a common integrated circuit device such as a static random access memory (SRAM) device.
Static memory devices such as static random access memory (SRAM) devices typically include an array of memory cells having a pair of complementary doped regions formed in the substrate, with the doped regions being connected to wordlines and the opposite ends of a pair of complementary bit lines, respectively. (The well known static memory devices having a multiplicity of pairs of complementary bit and word lines are usually referred to as CMOS static memory devices.) Each pair of complementary doped regions, referred to as the pair of cross-coupled inverters, forms a latch together with its opposite ends of a pair of complementary bit lines which provide access to the doped regions and, hence, to the latch. More specifically, when one of the doped regions is accessed by a high level (logic 1) bit line and the opposite end of the pair of complementary bit lines is coupled to a wordline having a high level (logic 1), the logic 1 state or data state of the accessed doped region is latched by the pair of cross-coupled inverters and, therefore, exists on the pair of complementary bit lines for future read-out operations. When one of the doped regions is accessed by a low level (logic 0) bit line and the opposite end of the pair of complementary bit lines is coupled to a wordline having a low level (logic 0), the logic

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